Digital phase-locked data recovery circuit
US5491729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1994 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.