Quantization step size adjusting circuit using edge detections
US5491761A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1991 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Oct 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T9/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quantization step size adjusting circuit using edge detection techniques for adjusting quantization step sizes in sampling an image signal to provide a digital signal by controlling an image compression ratio in dependence upon a pixel density representation (levels of sophistication) of an image. The quantization step size adjusting circuit comprises a coordinate converter for providing the image signal representative of a luminance signal and color difference signals, an edge detector for detecting edge values representative of peripheral pixels of a plurality of addresses of the image signal designated by control signals, a block formatting circuit for formatting the image signal into a plurality of image blocks having a predetermined size of pixels, and a circuit for controlling quantization step sizes of the image signal in dependence upon a determination edge values representative of peripheral pixels of a plurality of addresses of the image signal designated by the control signals and a determination of a selected scale factor in accordance with the pixel density representation of the image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.