Method and system for indexing the assignment of intermediate storage buffers in a superscalar processor system
US5491829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1995 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | May 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence. Results of execution from the selected one of the multiple scalar instructions are stored in the particular one of the intermediate storage buffers when the selected instruction is executed. The storage buffer index is used to determin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.