Integrated circuit chip testing apparatus
US5493237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | May 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0483
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This disclosure relates to testing apparatus (10), preferably an LGA burn-in test socket, for an integrated chip (28). The apparatus (10), arranged for mounting on a planar electronic device (46), such as a printed circuit board, includes a frame member (12) for mounting to the planar electronic device (46), where the frame member (12) includes a central opening (22) extending between first and second surfaces, and dimensionally sized to receive the chip (28). Recesses (35) are provided for receiving an electronic interface member (18) mounting plural flexible electrical connectors (106), such as an elastomeric connector, as known in the art, for engaging the traces or pads of the chip to the planar device during testing. Further, plural recesses (40) extend from at least the first surface, where each recess includes a compression spring (41). Positioned over and for engagement with the frame member is a floatably mounted force applying member (14) having first and second parallel surfaces. A central opening (75), concentric with the central opening ( 22) of the frame member (12) is present. Additionally, plural posts (62) extend from the second parallel surface for receipt in resp…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.