Gate circuit for hard driven GTO
US5493247A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1993 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Apr 28, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a circuit for hard driving a GTO, the conductor inductance (L1) and the internal inductance of the GTO (L2) form, together with a first capacitor (C1) situated in parallel via a switch (S), a series resonance circuit inside the gate circuit. In this connection, the chosen sizes of the first capacitor (C1) and of the first inductance (L1) are such that, if the first capacitor (C1) discharges via the two inductances (L1, L2), the gate current originating from the first capacitor (C1) exceeds half the value of a GTO anode current to be turned off within less than 5 .mu.s in the first quarter cycle of the series oscillatory circuit. Moreover, first means are provided which uncouple the first capacitor (C1) from the generation of the gate current after the first quarter cycle of the resonance circuit and allows the gate current to decay slowly in such a way that, at any time, it is greater than the tail current of the GTO. Finally, second means are provided in the form of a recharging circuit, which means are activated during the decay of the gate current and apply a holding current (V.sub.H) which is sufficient for blocking the gate (G) of the GTO after the decay of the gate current…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.