CMOS process and circuit including zero threshold transistors
US5493251A · kind A · utility
10Cited by
1References
21Claims
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Inventors
Key dates
| Filing date | Dec 2, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Dec 2, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/07
Abstract
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.