Modulator with biasing circuit to minimize output distortion
US5493257A · kind A · utility
5Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Aug 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/44
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A modulator for digital modulation is described to produce a modulated output from a voltage controlled oscillator in a phase locked loop during transmission of a random modulating input. The input voltage is applied to a coupling capacitor and when transmission ceases, the state of charge on the capacitor will not change because of a biasing circuit which comprises two resistors fed by a tri-state buffer which holds the input terminal of the capacitor at the average level between logic zero and logic one when no modulation is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.