Maximal deversity combining interference cancellation using sub-array processors and respective delay elements
US5493307A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 1995 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q3/2629
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A sidelobe canceler includes a main antenna, an array of sub-antennas, a subtractor having a first input connected to the main antenna, a main-array processor and M sub-array processors. The main-array processor multiplies the outputs of the sub-antennas with weight coefficients using correlations between the sub-antenna outputs and the subtractor output and combines the multiplied signals into a signal, which is coupled to the second input of the subtractor. The signal-to-noise ratio of the subtractor output is maximized by an adaptive matched filter. Each sub-array processor multiplies the sub-antenna outputs with weight coefficients using correlations between the sub-antenna outputs and a decision signal. The multiplied signals are summed to produce an output of each sub-array processor, which is combined with the outputs of the other sub-array processors into a first diversity-combined signal, the latter being combined with the matched filter output to produce a second diversity-combined signal. Intersymbol interference is removed by an adaptive equalizer from the second diversity-combined signal according to a decision error so that the decision signal is produced and applied …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.