High efficiency compact low power voltage doubler circuit
US5493486A · kind A · utility
23Cited by
12References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1995 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Mar 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
What is described is a high efficiency voltage doubler (100). The high efficiency voltage doubler (100), has a charge-pump capacitor (30), an inverter (18), a coupling capacitor (24), a complementary switch pair (16), a DC biasing circuit (102), a charging circuit (106), and an input circuit (108). This structure is adapted for use in an integrated circuit, and provides the advantage of maximizing voltage doubled power output and minimizing current consumption with a minimal number of components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.