Dual-port random access memory having memory cell controlled by write data lines and read enable line
US5493536A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Aug 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory circuit contains an array of memory cells, each of which contains a data latch formed of cross-coupled two inverters. First and second gate elements connected in series are placed between an output end of the latch and a reference point. Third and fourth gate elements connected in series are placed between the other output end and the reference point. Fifth, sixth and seventh gate elements connected in series are placed between the reference point and a read data line. During a write operation, while keeping the first and fourth gate elements and one of the second and third gate elements closed, a data to be stored is written in the latch through one of the pair of write data lines. During a read operation, while keeping the sixth and seventh gate elements closed, a stored data in the latch is read out through the read data line. Read and write operations can be performed without affecting the unselected memory cells, which reduces power dissipation during write and read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.