Image generator architecture employing tri-level fixed interleave processing and distribution buses
US5493643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1994 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | May 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09B9/301
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing. At this level, the displayed image is divided into small sub-regions that are assigned to tilers in a pseudo-random, but fixed manner. This levels the load across all pixel processors. Typically, tilers process a large contiguous area of the image. The present invention uses s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.