Memory architecture using page mode writes and single level write buffering
US5493666A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 1995 |
| Grant date | Feb 20, 1996 |
| Priority date | — |
| Expiry date | Jan 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0882
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture including a memory cache which uses a single level of write buffering in combination with page mode writes to attain zero wait state operation for most memory accesses by a microprocessor. By the use of such a memory architecture, the speed advantages of more expensive buffering schemes, such as FIFO buffering, are obtained using less complex designs. The memory architecture utilizes same page detection logic and latching circuitry and takes advantage of a feature built into industry standard dynamic RAMs, namely page mode writes, to perform writes to memory which allow the processor to be freed before the write is completed for the most frequently occurring type of write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.