Stuck fault detection for branch instruction condition signals
US5495598A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1993 |
| Grant date | Feb 27, 1996 |
| Priority date | — |
| Expiry date | Dec 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation. The branch condition is sent to the microprocessor as a signal pulse for a specified duration at a particular time, rather than by changing the level of the signal, thereby allowing communication of the branch condition over only one signal line but still providing for detection of faults in the VSLI gate array or faults inherent in the signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.