Dynamic random access memory device having first and second I/O line groups isolated from each other
US5497349A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 21, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Jun 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group. A first input/output gate circuit is connected to the first group of input/output lines and a second input/output gate circuit is connected to the second group of input/output lines, in which the first and second in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.