Cache testability circuit for embedded diagnostics
US5497458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1993 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Jul 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.