Universal address generator
US5497466A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Mar 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface system includes a processor unit 10 a local bus 11 coupled to the processor unit and interface circuitry 12 coupled to the local bus 11 for providing continuous generation of addresses on the local bus 11 or on a system bus 15. The local bus 11 may be a processor bus on a computer board while the system bus 15 may be an architectural bus standard such as Futurebus+. The interface circuitry 12 includes a universal address generator 14 that provides proper address generation on both system bus 15 and local bus 11. Also a method of generating addresses includes loading an address into an address register, saving the address if it is the first address, outputting the address to a local or system bus, incrementing the address, and repeating sequence at the loading step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.