Superscalar processor controlling fetching of instructions based upon number of empty instructions registers detected for each cycle
US5497496A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1994 |
| Grant date | Mar 5, 1996 |
| Priority date | — |
| Expiry date | Jul 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of instructions are read out from an instruction cache 1 for each cycle and temporarily stored in a second shift register SR2. The instructions stored in second shift register SR2 are transferred to empty positions of instruction registers IR0 to IR3 and fetched. An instruction decoder 3 selects instructions which can be processed in a parallel manner from the instructions stored in instruction registers IR0 to IR3 and supplies the same to any of processing units 4 to 7. A selector control circuit 12 controls the selection state of each selector 100 to 103, 200 to 203 based on a NUM signal indicating the number of empty instruction registers. The instructions stored in second shift register SR2 are thereby transferred to emptied instruction registers only. In this way, a new instruction is supplied to an empty instruction register as a supplement for each cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.