EPROM with trench in thick field oxide
US5498891A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | May 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An erasable-programmable read only memory (EPROM) allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM includes a semiconductor substrate, a field insulating layer defining a device formation region of the semiconductor substrate, a gate insulating layer and a floating gate formed on the field insulating layer and the field insulating layer. The EPROM further includes a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer so that one of the side walls of the trench insulating layer is self-aligned with the end face of the floating gate. A first interlaminar insulating layer covers the floating gate, and a control gate is located above the first interlaminar insulating layer. A second interlaminar insulating layer is formed over the control gate and a bit line is formed on the second interlaminar insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.