Low power flip-flop circuit and method thereof
US5498988A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Nov 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.