Memory cache with interlaced data and method of operation
US5499204A · kind A · utility
23Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1994 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Jul 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.