Memory defect detection arrangement
US5500823A · kind A · utility
48Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1994 |
| Grant date | Mar 19, 1996 |
| Priority date | — |
| Expiry date | Mar 31, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a static random access memory made up of six-transistor memory cells arranged in rows and columns, an arrangement for detecting open circuit or "soft" defects in the individual inverters of a memory cell includes lowering the supply voltage of a cell under test to overcome the clamping effect of a feedback inverter, applying input signal voltage changes to one of the bit lines associated with the cell, and testing for the expected voltage changes on the other bit line associated with the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.