Controllable width or gate
US5502401A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1995 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Apr 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controllable width OR gate employs a plurality of controllable OR gate cells. If the maximum width of the data to be ORed is N bits, then N-1 such controllable OR gate cells are needed. Each controllable OR gate cell 100 has four data inputs, OR0, ST0, OR1 and ST1, and a single control input CO. Each controllable OR gate cell has two outputs: ORout and STout. A first OR gate forms the OR of the OR0 and OR1 inputs unconditionally as the ORout output. A second OR gate forms the OR of the OR0 input and the ST1 input. Two pass gates are controlled in the opposite sense via the signal on control input C0 due to an invertor. If C0 is "1", then the output the second OR gate (OR0 OR ST1) is supplied to output STout. If C0 is "0", the ST0 input is supplied to output STout. Layers of the controllable OR gate cell can be used to from a wide controllable width OR gate. Each layer of cells is controlled by a corresponding bit of the control word. The STout of a single cell of a final layer forms the controllable width OR gate output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.