Circuit for decoding 2T encoded binary signals
US5502408A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1994 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Dec 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/497
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-type flip flop; a shift register having an input coupled to an output of the exclusive OR gate; a second D-type flip flop having an input coupled to the shift register; and, a second exclusive OR gate having inputs coupled to an output of the second D-type flip flop and to a tap of the shift register, the second exclusive OR gate having an output at which decoded input signals are reconstituted. The second D-type flip flop may be a constituent stage of the shift register, the inputs of the second exclusive OR gate being coupled to adjacent taps of the shift register. At least one of the adjacent taps is the output of the constituent stage formed by the second D-type flip flop. A gate arrangement is coupled to a plurality of taps of the shift register for decoding a predetermined bit pattern in the input signal, for example, a synchronizing component of a digitally recorded video signal played back to the data input terminal. The co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.