Variable length data decoder for use with MPEG encoded video data
US5502493A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1994 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | May 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention is embodied in a decoder for a video signal encoded according to the standard proposed by the Moving Pictures Expert Group (MPEG) of the International Standards Organization (ISO). This decoder employs four sets of processors, each set containing three processors that operate concurrently to decode the MPEG-2 video signal. A variable length decoder processes the input stream to decode the variable length encoded data. The operations performed by this decoding processor change depending on the type of data being decoded. These changes are implemented using a master Digital Signal Processor (DSP) which is programmed according to the MPEG-2 syntax. The data decoded by the VLD processor is either video data or control data. The control data is divided into two types, control data needed to reproduce the image and control data that describes the bit-stream. The control data needed to decode the image is passed to a control DSP while the control data which describes the bit-stream is passed to the master DSP. To ensure that the entire system can operate with sufficient speed to decode an image in real time, this group of three processors is duplicated four times in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.