Single cycle flush for RAM memory
US5502670A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 30, 1994 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Nov 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.