Semiconductor memory device having a multi-bit input/output configuration which is capable of correcting a bit failure
US5502675A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1994 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Jun 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cell arrays and a plurality of word lines and bit lines. The semiconductor memory device has a plurality of row driving circuits for simultaneously activating a plurality of word lines, and a plurality of column driving circuits for simultaneously and independently activating a plurality of column selection lines to simultaneously select a plurality of bit lines. A data selector selects, from the memory cells selected by the word and bit lines, a memory cell selected by different word lines and bit lines. Thus, a plurality of bits are read out or written into the memory cell arrays in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.