Sense amplifier with pull-up circuit for accelerated latching of logic level output data
US5502680A · kind A · utility
Inventors
Key dates
| Filing date | Feb 16, 1995 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Feb 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1and din2, and generates, in response to a first control signal .PHI..sub.1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal .PHI..sub.2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal .PHI..sub.0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, .PHI..sub.1 and .PHI..sub.2, is such that the second control signal .PHI..sub.2 is activated LOW after a finite period following the initial activation of the first control signal .PHI..sub.1 . The third control signal .PHI..sub…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.