Delay test coverage without additional dummy latches in a scan-based test design
US5502731A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1994 |
| Grant date | Mar 26, 1996 |
| Priority date | — |
| Expiry date | Aug 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318586
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; soding this list in the order of number of outputs controlled, i.e. touched in the forward trace: listing each unique combinational circuit output: sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of tile same circuit outputs: when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.