Compact dual function adder
US5504698A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1994 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | May 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact dual function adder circuit for providing both an addition operation for adding an input m-bit word to an input n-bit word, wherein m<n, and an increment operation for incrementing the input n-bit word, the dual function adder comprising a n-bit incrementer circuit, wherein the n-bit incrementer includes a first m-bit incrementer and a second n-m)-bit incrementer to provide a n-bit incrementer output sum. The n-bit incrementer output sum comprises an m-bit incrementer output sum from the m-bit incrementer and a n-m)-bit incrementer output sum from the n-m)-bit incrementer. The compact dual function adder also comprises a combined adder circuit, the combined adder comprising a first m-bit full-adder, a n-m)-bit decrementer, and an adder select logic circuit, wherein the adder select logic receives an adder carryout bit from the m-bit full-adder and a bit<15> of the input m-bit word to control an operation of the adder select logic to generate either an increment operation, a decrement operation, or a bypass operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.