Parallel processing with improved instruction misalignment detection
US5504923A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1994 |
| Grant date | Apr 2, 1996 |
| Priority date | — |
| Expiry date | Sep 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Availability flag registers are used for storing flags ia1-ia4 indicating the availability of instructions IR1-IR4 stored in an instruction register. The flags ia1-ia4 are controlled in accordance with misalignment information which represents the degree of an address accessing an instruction cache being shifted from a four word boundary. Upon determining whether or not issuance of an instruction from instruction decoder is possible, it is determined to be unissuable if an availability flag corresponding to each instruction is off. A logic structure for nullifying an instruction stored in an instruction register, when an address in accessing instruction cache 1 is shifted from the four word boundary is implemented without providing the instruction register with a resetting function, and thus a circuit for implementing this logic can be constructed with a reduced number of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.