Static ram having an active area with a tapered bottom surface
US5506435A · kind A · utility
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3References
2Claims
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Assignee
Inventors
Key dates
| Filing date | Mar 29, 1995 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Mar 29, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.