Output enable structure and method for a programmable logic device
US5506517A · kind A · utility
18Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1994 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Nov 21, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output enable structure and a method for providing output capability to an input/output cell of a programmable logic device are shown. In one embodiment, one of two global output enable signals, a test output enable signal, and two product term output enable signals is selected for controlling an output buffer of an I/O cell. Additional pin-out flexibility is provided by routing the input signal received at an I/O pin to neighboring I/O cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.