Sampling circuit for analog signals
US5506525A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1992 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Jul 29, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sampling circuit which obtains a level of sampled-and-held signal which is determined with respect to a well-determined reference level V0, even though the input signal is a useful signal referenced with respect to a low-stability reference level. This is the case in particular for sampling of signals derived from charge-transfer photosensitive devices for which the dark level can vary. The circuit includes a sample-and-hold device (EB1) and an input via a capacitor (C1), with a reset circuit which periodically charges the capacitor (C1) to a value which is roughly the difference between the (variable) input reference level and the (fixed) output reference level. According to the invention, it is provided that the reset circuit comprises a looped amplifier (AD1) in which the loop (B1, EB2, B2) is designed to introduce a voltage level shift equal to the shift introduced intrinsically by the sample-and-hold device (B1, EB1, B2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.