Bias circuit for depletion mode field effect transistors
US5506544A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1995 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Apr 10, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/301
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier (10) receives a bias voltage to the gate of a depletion mode field effect transistor (12). In one embodiment, a bias circuit (20) offsets (22) the bias voltage from a power supply potential (26) to maintain substantially constant drain current over a range of threshold voltages (34,36,38) caused by process and temperature variation. In an alternate embodiment, a transistor (58) in the bias circuit (50) provides an incremental current flow to compensate the bias voltage of the MESFET for variation in threshold voltages. The bias circuit is applicable to other depletion mode field effect transistor circuits having a negative threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.