Provision of FIFO buffer in RAM
US5506747A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1994 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Dec 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
FIFOs having various depths are provided in a RAM in a plurality of groups. For each group, stored numbers B and D determine a base address 2.sup.B in the RAM for the group and a depth 2.sup.D of each FIFO in the group. Each FIFO is identified by a respective FIFO identity having a most significant "1" bit whose position identifies the respective group of FIFOs, less significant bits identifying the respective FIFO in the group. A count C is provided which is common to all of the FIFOs for identifying a respective location in each FIFO. Each FIFO in the RAM is addressed with an address comprising a sum of the base address 2.sup.B, a product of said less significant bits multiplied by 2.sup.D, and a number C mod 2.sup.D, using the stored numbers B and D determined by the respective FIFO identity. The sum can be provided by an OR function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.