Reconfigurable multi-user buffer memory particularly for signal processing system
US5506815A · kind A · utility
39Cited by
8References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 19, 1995 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Jan 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer memory system provides independent memory blocks, each with independent addressing and data paths, for a processor and input and output devices. The processor can configure the data paths so that an input device can initially supply data to a first memory block. The processor can then assign a second block for input and operate on the data in the first block. The processor can store the results of the process in a third block that has been assigned to an output device. The memory blocks and the associated data paths can paired for operating with a processor with a wider data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.