Error correction and channel restoration apparatus for T1 digital links
US5506956A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 7, 1993 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Apr 7, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/0079
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Apparatus, operating in a digital communication system, for interconnecting a primary or a secondary network to an output port. The primary and secondary networks are redundant networks having point-to-point topologies (125, 130) or point-to-multi-point topologies (210, 215). When connected in a point-to-point network topology that supports extended superframe format (ESF), the apparatus functions as an error correction switch and; when connected in a point-to-multi-point network topology, the apparatus functions as a DS1/0 protection switch. In its receiver aspect, the apparatus stores frames of digital data received from each of two redundant networks, inspects certain error codes contained in the received data and, in response to these error codes, selects the digital data originating from one of the networks that does not exhibit an error code. The data selection process uses a time-slot interchanging (TSI) technique. The selected data is subsequently transferred to downstream digital signal processing equipment. In its transmitter aspect, the apparatus transmits replicated versions of digital data supplied by digital transmission equipment onto both redundant networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.