Synchronization for out of order floating point data loads
US5506957A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1995 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Jun 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system that allows the continuous accessing of data on a floating point processor unit (FPU), by providing two data ports and corresponding buses between the data cache and the FPU. Further, synchronization between the fixed point unit (FXU), which provides the addresses, and the FPU is provided so that data can be loaded in the event of a data cache miss. This synchronization allows data to be transferred from the DCU to the FPU independent of an error condition (cache miss) on one of the buses. If a cache miss occurs that affects a first one of the buses, then the instruction corresponding to this data is held. Subsequent floating point data is received by the FPU on the second bus not subject to the miss. Synchronization signals include, load ready (LD1.sub.-- RDY) indicating to the FPU that data is on the bus and ready to be moved to the FPU and load not ready (LD1.sub.-- NRDY) that means a floating point load has executed successfully in the FXU, but due to a cache miss, the data is not yet available to the FPU. The FXU sends an address, along an address bus corresponding to the data bus not affected by the miss, for data in the cache. Thus, even in the case of a data cache …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.