System with multiple interface logic circuits including arbitration logic for individually linking multiple processing systems to at least one remote sub-system
US5506964A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1992 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Apr 16, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing and transmission network includes plural information processing systems and shared sub-systems remote from the information processing systems. Each shared sub-system includes an I/O bus and a plurality of I/O bus interface logic circuits coupled to the bus. Each interface logic circuit is coupled to one of the system processing devices via a bidirectional fiber optic link, and thereby couples its associated processing device to the I/O bus. Further fiber optic links couple each system processing device to the I/O bus of each remaining sub-system through an associated I/O bus interface logic circuit. Each sub-system further includes multiple I/O devices, each device coupled to a device controller which in turn is coupled to the I/O bus. The bus interface logic circuits and device controllers incorporate arbitration circuitry and communicate with one another via their associated I/O bus, thus to resolve contentions for control of the bus at the sub-system level rather than at the system processor level. These features provide a network with a high degree of redundancy, substantially reduced data access times, and flexibility in network configurations. Regardless of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.