Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures
US5506967A · kind A · utility
45Cited by
13References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 15, 1993 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Jun 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a time-shared bus computer system with processors having cache memories, an adjustable invalidation queue for use in the cache memories. The invalidation queue has adjustable upper and lower limit positions that define when the queue is logically full and logically empty, respectively. The queue is flushed down to the lower limit when the contents of the queue attain the upper limit. During the queue flushing operation, WRITE requests on the bus are RETRYed. The computer maintenance system sets the upper and lower limits at system initialization time to optimize system performance under maximum bus traffic conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.