Method for minimizing the time skew of electrical signals in very large scale integrated circuits
US5507029A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1995 |
| Grant date | Apr 9, 1996 |
| Priority date | — |
| Expiry date | Jan 11, 2015 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for minimizing the time skew between signals traveling through various multi-cycle path nets linking one or several VLSI packages that includes a plurality of IC chips interconnected to each other. The method includes equalizing differences between the early and the late mode slack for each of the multi-cycle nets to decrease the joint probability of failure; maximizing the time balance between the early and the late mode slack; balancing over all the nets the difference between the early and the late mode slack, minimizing in the process statistical variations within the mode slack pair; and compensating for asymmetries between rising and falling switching times using the mode slack pair. The method allows multi-cycle path nets have their transmission line length confined between a maximum and a minimum length, which in turn minimizes the skew between signals in each of the nets, decreases cycle time and .improves the overall performance of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.