Bitline level insensitive sense amplifier
US5508643A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1994 |
| Grant date | Apr 16, 1996 |
| Priority date | — |
| Expiry date | Nov 16, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier for detecting the difference in voltage between two bitlines of a memory circuit. The sense amplifier is comprised of a differential amplifier which is coupled to the two bitlines and generates an output signal based on voltage levels sensed in the bitlines. The differential amplifier is coupled to V.sub.CC and ground through an active load and a current source respectively. To address the problem of increased common mode voltage levels found in the bitlines, a pair of transistors are connected in parallel across the active load to V.sub.CC and the differential amplifier. The gate of one of the transistors is coupled to one of the bitlines and the gate of the other one of the transistors is coupled to the other one of the bitlines. With these two transistors coupled in parallel across the load as described, the differential amplifier has increased immunity to elevated common mode levels found in the bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.