Write recovery time minimization for Bi-CMOS SRAM
US5508964A · kind A · utility
1Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 8, 1993 |
| Grant date | Apr 16, 1996 |
| Priority date | — |
| Expiry date | Jan 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for minimizing write recovery time in a Bi-CMOS SRAM by equalizing the bit-line voltages during a read access. A P-channel device whose drain, source and gate are connected to bit, bit-bar, and the write control signal, respectively, indirectly equalizes the bit-lines by equalizing the base voltages of the NPN bit-line load devices only when the column is selected for read access. This technique takes advantage of the current gain of the NPN transistor from the base to the emitter to provide fast bit-line equalization immediately following writes, thus minimizing the write recovery time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.