Multilayer antifuse with intermediate spacer layer
US5510629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | May 27, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure for an improved antifuse in an integrated circuit having a sacrificial layer under a programming layer which forces a conductive link upon programming to be formed away from corner regions of the via structures. The method includes the unique step of forming an improved aperture or via with sides through an inter dielectric layer where the antifuse is to be located. The improved aperture or via exposes a portion of a metal interconnection line through a portion of sacrificial layer located away from the inter dielectric layer sides. Such improved method of forming the antifuse also provides a superior antifuse structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.