Parallel architecture for a high definition television video decoder having multiple independent frame memories
US5510842A · kind A · utility
51Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | May 4, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A parallel decoder for an MPEG-2 encoded video signal includes a deformatter which separates the input bit stream into multiple portions, each representing a respectively different section of the HDTV image. The separate portions are processed in parallel by respective decoders. In order to perform motion compensated processing, each of the four decoders includes a memory that holds data representing the entire image. Each decoder provides its decoded output data to all of the decoders to maintain the data in the respective memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.