Flicker reduction and size adjustment for video controller with interlaced video output
US5510843A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Sep 30, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0414
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for reducing flicker and/or vertically scaling an interlaced video image. In a first embodiment, a sequence controller selectively addresses a video memory to retrieve pixel data from adjacent scan lines. The pixel data is multiplexed and converted into RGB data in a look up table and stored in upper and lower latches as upper and lower pixel data. The upper and lower pixel data is then weighted using a predetermined weighting scheme to produce hybrid pixel color data for an even or odd field. By reducing relative contrast between even and odd field lines, flicker is reduced. In a second embodiment, vertical resolution is reduced, for example, from 480 lines to 400 lines, by applying a series of weighting schemes or filters to weight data from six input lines into five output lines. To reduce flicker in the output lines, data from adjacent lines may weighted to reduce relative contrast. Due to the 6:5 reduction, a discontinuity in the output lines may exist where adjacent line data is not weighted. Luminance data from a third adjacent line may be weighted with pixel data from adjacent lines to reduce flicker at the discontinuity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.