Memory system including local and global caches for storing floating point and integer data

US5510934A · kind A · utility

Assignee

• Silicon Graphics, Inc. · US

Inventors

• John Brennan · Wyomissing, US
• Peter Hsu · Fremont, US
• William A. Huffman · Los Gatos, US
• Paul Rodman · Palo Alto, US
• Joseph T. Scanlon · Sunnyvale, US
• Man Kit Tang · Saratoga, US
• Steve J. Ciavaglia · Williston, US

Key dates

• Filing date: Dec 15, 1993
• Grant date: Apr 23, 1996
• Expiry date: Dec 15, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0831
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.