Method and apparatus for correction errors in a memory
US5511078A · kind A · utility
12Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1993 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Nov 18, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method and apparatus for correcting one B-bit block in error in a memory organized in words comprising N B-bit blocks consist of appending to the data bits to be written into the memory words a limited number of error correction bits computed from a depopulated parity check matrix which gives the capability of only correcting one block in error and improving the memory failure rate by cyclically reading each word, correcting a block found in error if any and writing the corrected data bits with the corresponding error correction bits in place of the read word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.