Clock synchronization control check system
US5511091A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 1994 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Jun 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0091
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock synchronization control check system for a digital baseband signal receiver which digitally provides a phase error to digital data generated by a digital modulator without the need for conversion of the digital data to analog data so that clock synchronization control in its demodulating section can be checked easily and precisely. In the system, a digital filter is used to suppress inter-symbol interference, and a set of filter coefficients for the digital filter is shifted along the time axis of an impulse response so as to provide a plurality of filter coefficient sets. By selecting one of the coefficient sets, a desired phase shift is given to the digital data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.