Polycyclic timing system and apparatus for pipelined computer operation
US5511181A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1993 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Apr 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A polycyclic timing system and an apparatus for pipelined computer operation comprises a master state machine and a slave state machine. The master state machine produces a plurality of control signals in response to a clock signal. The master state machine comprises an oscillator, a plurality of data storage elements, and a next state feedback network. The oscillator is used to produce a clock signal that triggers the storage elements. The next state feedback network determines the control signals to output based on the current output data storage elements using logic in the next state feedback network. The slave state machine receives the control signals and uses them to produce several asynchronous pulse streams. The slave state machine preferably comprises a plurality of pulse forming state machines and a plurality of pulse transmission amplifiers. Each of pulse forming state machine is an edge to pulse converter that produces at least one pulse in response to a control signal received from the master state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.